1. Field of the Invention
The present invention relates to a circuit pattern designed for test of a semiconductor circuit in which each of a plurality of circuits formed on a semiconductor wafer according to individual design conditions are the object of electrical measurement and evaluation.
In particular, the present invention relates to the technique of evaluation of the production of semiconductor used when a difference between a design pattern and a circuit pattern formed on a wafer comes out according to design condition so that the correction or reformation of design pattern designed for the production of semiconductor is needed.
2. Description of the Related Art
In recent years, higher integration and function were being requested for various LSI (large scale integrated circuits) typified by ASIC (application specific integrated circuits) from the tendency for the electrical device to be made highly functional, lightweight, thin, short and small. Namely, it is desired to make chip size as small as possible to realize high function for LSI such as ASIC.
The above-mentioned LSI such as ASIC is formed through several steps for the production of semiconductor device of forming figure data which is also called xe2x80x9cpattern dataxe2x80x9d for the production of photomask pattern through functional design, logic design, circuit design and layout design, forming photomask using the figure data and thereafter transferring pattern of the photomask onto a wafer by demagnification projection.
Photomask is generally formed using the above-mentioned figure data (pattern data) and through steps of writing the figure data on photosensitive resist put on the shading film of photomask substrate (it is also called xe2x80x9cphotomask blanksxe2x80x9d) by means of electron beam exposure system or aligner of photo such as excimer wavelength, developing and etching.
Namely, photomask having a desired metallic thin film pattern can be obtained through the following steps of: applying photosensitive resist on a photomask substrate provided with a shading metallic thin film on a one face of a glass substrate, and drying the photosensitive resist; applying ionizing radiation only to the given area by means of aligner to form a latent image; developing the photosensitive resist with latent image to obtain a resist pattern with a desired shape corresponding to the area to which ionizing radiation is applied; and working the metallic film into the shape of resist pattern using the resist pattern as etching-proof resist by etching.
In this case, when a pattern of photomask is transferred to a wafer by demagnification projection, the photomask is also called xe2x80x9creticle maskxe2x80x9d.
In such a manner, a circuit pattern is formed on a wafer by transferring a pattern of photomask on a wafer by demagnification projection. However, electrical property of the circuit pattern formed on a wafer is not always determined by only the two-dimensional shape of circuit pattern, but by the three-dimensional shape of circuit pattern. Therefore, it has been carried out to form a test circuit pattern for evaluation on a wafer and evaluate the electrical property of the test circuit pattern.
Further, in a former case which can be based on the assumption that the formed circuit pattern of LSI is not made so small that a test design pattern of photomask is faithfully formed on a wafer, a scale of a test circuit pattern is small, in which the number of test cells used for the object of the specific evaluation was within several tens.
However, recently, a size of the pattern exposed (a size of the pattern exposed on a wafer) was made finer as the integration of LSI is made higher and higher so that a size of the pattern exposed approached the wavelength of rays or became smaller than the wavelength of rays exposed. Therefore, a deformation of the exposed shape called xe2x80x9coptical proximity effectxe2x80x9d came to arise when a pattern of photomask is transferred on a wafer through demagnification projection. As a result, there was a case where a pattern was not formed on a wafer with the same size as another pattern according to design conditions, even if the pattern is a pattern having the same size as another pattern on photomask. This influences the electrical property of circuit formed on a wafer. Accordingly, the necessity appeared that test circuit patterns must be formed both on a wafer and on a photomask, according to design conditions.
The test circuit patterns enables to appropriately correct a pattern on a photomask or to appropriately reform a design pattern on a photomask.
Further, referring to the drawings, the necessity of a circuit pattern designed for test on a wafer (hereafter, it is called xe2x80x9ctest design circuitxe2x80x9d) is explained concretely.
As shown in FIG. 7(a), in the design of semiconductor circuit, two-dimensional design pattern 201 is formed, wherein as shown in FIG. 7(b), a circuit pattern formed on a semiconductor wafer becomes a figure pattern (it is called xe2x80x9ccircuit patternxe2x80x9d) 202 having the sectional shape different from the design pattern (a).
A section taken on line D1-D2 of design pattern 202 formed on a wafer shown in FIG. 7(b) has the shape of section shown for example indicated by numeral 204 shown in FIG. 7(c).
In order to determine the electrical property of a pattern formed on a semiconductor wafer according to the three-dimensional shape thereof, it is necessary to design a test design pattern 210 as shown in FIG. 8 as the shape of pattern on a photomask and to form a pattern on a semiconductor wafer wherein the electrical property of the pattern formed on a semiconductor wafer is evaluated.
In FIG. 8, numeral 211 designates a circuit portion of the object of evaluation and numeral 212 designates a wiring portion.
Further, in FIG. 8, numeral 213 and 214 designates pads, which are connection portions between a semiconductor wafer and an electrical measuring instrument, in which pads necessitate a least areas of 80 xcexcm square on a semiconductor wafer for physical contact of the pads with a needle.
Pads 213, 214 are connected with circuit portion 211 wherein the object of evaluation of test pattern 210 through wiring portions 212 which are wirings with secure thickness for the electrical connection to the circuit portion 211.
Design rule of semiconductor circuit is determined by evaluating the electrical property of a pattern on a semiconductor wafer by the test design circuit pattern, by which design based on the two-dimensional information is made possible.
However, from the latter half of the 1990s, the meaning of xe2x80x9ctest design circuit patternxe2x80x9d begins to change, as the technique for forming a pattern with a size smaller than the wavelength of rays from semiconductor exposure is extensively carried out.
FIG. 9(a) shows design patterns including figures with the size smaller than the wavelength of rays from a semiconductor exposurer or exposure device. FIG. 9(b) shows an example of a pattern formed on a semiconductor wafer by projecting the design pattern onto a semiconductor wafer by demagnification projection.
This is called optical proximity effect wherein a pattern cannot be formed on a semiconductor wafer as the design pattern.
In FIG. 9(a) numerals 221, 222 and 223 designate design patterns. In FIG. 9(b), numerals 224, 225 and 226 designate patterns on a wafer corresponding to design patterns 221, 222 and 223, respectively.
FIG. 10(a) shows patterns provided with correction patterns at corners thereof so as to reduce deformations caused by optical proximity effect. FIG. 10(b) shows patterns with the shape being near to the objective shape of pattern formed by projecting the design patterns shown in FIG. 10(a) onto a semiconductor wafer by demagnification projection, which is called xe2x80x9coptical proximity effect correction techniquexe2x80x9d.
In FIG. 10(a), numerals 241, 242 and 243 designate design patterns. In FIG. 10(b), numerals 244, 245 and 246 designate patterns formed on a wafer corresponding to design patterns 241, 242 and 243.
In such a manner, actual patterns formed on a semiconductor wafer are slightly different from the corresponding design patterns. This explanation is based on the figure pattern of a photomask formed from a design pattern not being formed faithfully to the design pattern. Thus, in this stage, the meaning of xe2x80x9ctest design patternxe2x80x9d began to change.
Namely, a former test design circuit pattern was supposed to be formed faithfully on a semiconductor wafer, and the electrical property of circuit pattern formed on a semiconductor wafer was extracted on the basis of the above-mentioned assumption.
However, when a figure with a size smaller than the wavelength of rays from a semiconductor exposurer is formed, a difference between a circuit pattern formed on a semiconductor wafer and a test design pattern arises, according to many conditions such as arrangement and density of figures in the test design pattern, a method of optical proximity effect correction, and a method of forming phase shift mask data.
Therefore, the above-mentioned conditions are set as much as possible in a test design circuit pattern, and the object thereof became to evaluate how circuit patterns are formed on a semiconductor wafer.
Referring to FIGS. 11(a)-11(c), this is explained.
FIGS. 11(a), (b), (c) show circuit patterns formed on a semiconductor wafer (they are also called xe2x80x9ctest cellsxe2x80x9d). If circuit portions 251, 252, 253 for which electrical measurement and evaluation are carried out are formed on a wafer according to design patterns, the same circuit patterns should be formed so that the same electrical properties should be obtained for the respective circuit portions. However, optical proximity effect seen when demagnification projection is made is brought about differently according to the arrangement of figures and densities thereof in a design pattern for the respective circuit patterns. Therefore, circuit portions 251, 252, 253 cannot be formed on a wafer according to a design pattern so that the same circuit patterns result. Therefore, the same electrical properties cannot be obtained for the respective circuit portions.
Therefore, it is needed to consider pattern density in design patterns. Accordingly, varied design circuit patterns for test of a semiconductor circuit are needed in which distances between circuit figures formed on a wafer are varied little by little.
Namely, it is needed to form test design circuit patterns on a semiconductor wafer through design patterns for test by demagnification projection and electrically connecting a measuring instrument to the test design circuit patterns to evaluate the electrical properties thereof.
In FIGS. 11(a)-11(c), numeral 212 designates a wiring portion, numeral 213 designates an input signal pad, numeral 214 designates an output signal pad, and numeral 252a and 253a designates additional pattern portions.
As mentioned hereinabove, up to now, when it was not so much progressed to make wirings of circuit highly dense and minute, the assumption was possible that design circuit patterns for test are formed on a semiconductor wafer faithfully to test design patterns. Therefore, the scale of test design patterns was very small. The number of test cells used for the specific subject of evaluation was dozens at the most. In recent years, it has been progressed to make wirings of circuit highly dense and minute so that optical proximity effect and the correction of optical proximity effect are needed for the production of circuit formed on a wafer. Therefore, the shape of patterns formed on a semiconductor changes according to design conditions. As a result, it became difficult to obtain desired shape of patterns.
Accordingly, in recent years, a design circuit pattern for test including conditions of design as much as possible has come to be needed.
According to this, it is an object of the present invention to provide design circuit patterns for test having many test patterns corresponding to design conditions, in which optical proximity effect and the correction of optical proximity effect are needed for the production of circuits on a wafer, wherein the design circuit pattern for test makes it possible to evaluate each test pattern at the practical level.
Namely, if a pattern formed on a semiconductor is provided with test pads wherein the test pads are needed at least two for every individual test cell in case of a pattern formed on a semiconductor wafer being a minute figure with the size of pattern under 0.2 xcexcm, the ratio of area of test pads to the area of test design pattern becomes predominant. Therefore, a test design pattern in which many design conditions are included is not practicable because of limitations of the whole area of the test design pattern. Further, when a circuit pattern with many design conditions is formed on a semiconductor wafer in such a way, many delicate works such as the connection of respective pads with an electrical measuring instrument through a needle are needed. Therefore, there is a problem that evaluation works are increased. The present invention provides a design circuit pattern for test to solve the above-mentioned problems.
An arrangement for testing a design circuit pattern applied to a semiconductor circuit for the present invention comprises a circuit pattern having a plurality of circuits formed on a semiconductor wafer wherein each of the circuits is designed for test according to an individual design condition as the object of electrical measurement and evaluation. The circuit pattern on the semiconductor wafer comprises a group of two or more test cells, wherein each of the test cells formed from the individual design conditions corresponding to respective ones of the design circuit patterns for the object of electrical measurement and evaluation are formed according to individual conditions and have a switch or switches connected at one end or both ends thereof. A decoder generates on/off signals to the switch or switches provided within the group of test cells for specifying an evaluated test cell chosen from the group of test cells for electrical measurement and evaluation. One or more of address pads input an electrical signal specifying the evaluated test cell to the decoder. An input pad provides an electrical input signal to the evaluated test cell. An output pad receives an electrical output signal from the evaluated test cell. One or more of the contrastive evaluated test cells are provided corresponding to the group of test cells. A contrastive evaluated input pad directly connected with one end of the contrastive evaluated test cell and provided for each of the contrastive evaluated test cells provides an input signal and a contrastive evaluated output pad directly connected with the other end of the contrastive evaluated test cell and provided for each of the contrastive evaluated test cells outputs an electrical signal.
An arrangement for testing design circuit patterns applied as a semiconductor circuit of the present invention comprises a circuit pattern having a plurality of circuits formed on a semiconductor wafer wherein each of the circuits is designed for test according to an individual design condition as the object of electrical measurement and evaluation. The circuit pattern on a semiconductor wafer comprises a group of two or more test cells formed by individual design conditions corresponding to respective ones of the design circuit patterns for the object of electrical measurement and evaluation. A switch or switches are connected with one end or both ends of the test cells. A decoder for generating an on/off signal to the switch or switches is provided with the group of test cells for specifying an evaluated test cell chosen from the group of test cells for electrical measurement and evaluation. A counter circuit generates an electrical signal for a decoder specifying the evaluated test cell. A reset pad initializes the counter circuit. A clock pad operates the counter circuit. An input pad provides an electrical input signal to the evaluated test cell and an output pad receives an electrical output signal from the evaluated test cell. One or more contrastive evaluated test cells are provided in addition to the group of test cells. A contrastive evaluated input pad directly connected on one end of the contrastive evaluated test cell and provided for each of the contrastive evaluated test cells inputs an electrical signal. An output pad directly connected with the other end and provided for each of the contrastive evaluated test cells receives an electrical signal.
Further, in the above-mentioned invention, the circuits of the object of electrical measurement and evaluation arranged according to individual condition are characterized by additional circuit patterns corresponding to additional design conditions arranged around the existing respective circuits.
By having the above-mentioned construction, the present invention makes possible the provision of a design pattern for test having many test circuit patterns corresponding to design conditions, wherein each test circuit pattern can be evaluated at practical level.
The present invention includes a construction in which a switch is provided at a measuring end of individual test cells and a decoder is provided in which a signal for selecting an individual test cell is generated outside of a group of test cells and the desired test cell is specified by the signal sent through a switch provided at a measuring end of the individual test cell. Therefore, many test cells can be arranged in a test design pattern, while the number of pads can be lessened, so that a large area is unnecessary for the whole circuit pattern tested.
In the present invention, it is sufficient to have two pads for input and for output, since the mutual measuring end of the respective test cells is possible for measurement of electrical properties.
Further, by providing an input signal to a decoder from an address pad or a counter, if the number of test cells is tn, it is sufficient for the input signal of the decoder to be log 2 (tn).
Further, the present invention comprises, in addition to a group of test cells, one or more of contrastive or contrasting evaluated test cells, a contrastive evaluated input pad connected at one end of the contrastive evaluated test cell and provided for each of the contrastive evaluated test cells for providing electrical signal, and a contrastive evaluated output pad connected at the other end of the contrastive evaluated test cell and provided for every one of the contrastive evaluated test cells for obtaining electrical signal. Accordingly, it is possible to make the measurement and evaluation considering a change of electrical properties caused by a switch when determining electrical properties or a change of electrical properties caused by the mutual measuring end of the respective test cells.
Particularly, in the present invention, no change in a contact point of a needle connected with a measuring instrument with a pad is needed, when determining electrical properties.
Further, in case of the construction of the present invention in which a decoder and a counter are used, the operation of the counter can be associated with a test cell of the object of measurement. Accordingly, it becomes easy to make the statistical analysis on the basis of result of measuring of electrical properties of more test cells.